Transport offload engines (TOE) include technology that is gaining popularity in high-speed systems for the purpose of optimizing throughput, and lowering processor utilization. TOE components are often incorporated into one of various printed circuit boards, such as a network interface card (NIC), a host bus adapter (HBA), a motherboard; or in any other desired offloading context.
In recent years, the communication speed in systems has increased faster than processor speed. This has produced an input/output (I/O) bottleneck. The processor, which is designed primarily for computing and not for I/O, cannot typically keep up with the data units flowing through the network. As a result, the data flow is processed at a rate slower than the speed of the network. TOE technology solves this problem by removing the burden (i.e. offloading) from the processor and/or I/O subsystem.
Prior art FIG. 1 illustrates a system 100 including both a host processor 102 and a transport offload engine 104, in accordance with the prior art. In use, the processor 102 generates data lists 106 [i.e. scatter-gather lists (SGLs), etc.] for identifying a location in memory 110 where data resides which is to be communicated via a network 116. As shown, the data lists 106 include an address where the data may be found, as well as an associated length.
In use, the processor 102 transmits the data lists 106 to the transport offload engine 104. Armed with such data lists 106, the transport offload engine 104 retrieves the data from the memory 110 and stores the same in a buffer 112, where the data waits to be communicated via the network 116.
To track the various network connections or sockets over which the data is communicated via the network 116, the transport offload engine 104 further employs control blocks 114, which may each include various information associated with a particular network connection or socket.
Thus, to receive a large amount of data via the network 116, the memory required to store data lists 106 and control blocks 114 as well as the buffer 112 may become excessively large. Unfortunately, a large memory can not be implemented in a cost-effective manner on an integrated-circuit transport offload engine 104, since integrating on-board memory on the transport offload engine 104 is costly in terms of silicon die area, for example.
There is thus a need for a more cost effective-technique for transmitting data in a network using data lists (SGLs, etc.).